In recent years, a semiconductor device, in which a nonvolatile memory cell array and a logic circuit for operating at high-speed are mounted on the same chip, have been in practical use. The logic circuit for performing high-speed processing is applied to, for example, a CPU or a ROM, and is operated at a low voltage to increase the carrier mobility. Meanwhile, a transistor used as the storage for the nonvolatile memory and a transistor used for selecting memory cells are constituted by high voltage transistors. Furthermore, analog circuits such as the amplifying circuit, the transmission circuit, and the power source circuit are also constituted by high voltage transistors.
The following problem arises when a side wall (hereinafter, simply referred to as “side wall” or “SW”) spacer of a low voltage transistor and a side wall (SW) of a high voltage transistor are fabricated substantially simultaneously in a single process by the same procedure. As illustrated in FIG. 1, a low voltage transistor LVTr is miniaturized for the purpose of implementing high-speed switching operations. If a side wall 110 of the high voltage transistor HVTr has the same width as the side wall (SW) of the low voltage transistor LVTr, a length d in the high voltage transistor HVTr is reduced. Specifically, the length d is the length between the leading edge of a source/drain extension 106, which is a low-concentration diffusion layer, and the leading edge of a source/drain 108, which is a high-concentration diffusion layer. As a result, the concentration profile becomes steep near the junction on the drain side, and the generation efficiency of impact ionization is enhanced. Accordingly, as illustrated in FIG. 2, the junction withstand voltage and the snapback withstand voltage on the drain side are decreased.
Impact ionization is a phenomenon in which the gate current and the source/drain current rapidly increase when an electron is accelerated to a high-energy state by a high electrical field and collides with an electron in a valence band, and an electron-hole pair is formed. As illustrated in FIG. 2, when the breakdown voltage of the high voltage transistor HVTr, which is the standard voltage, is greater than or equal to 10 V, the voltage BVds at which snapback occurs (breakdown voltage between source and drain) decreases to less than 10 V, due to the narrow SW width. As illustrated in the example of FIG. 1, the side wall 110 in both the high voltage transistor HVTr and the low voltage transistor LVTr has a two-layered structure including an oxide film 110A and a nitride film 110B. The same problem as described above arises when the side wall 110 has a single-layered structure or a three-layered structure, as long as the side walls on the high-voltage operation side and the low-voltage operation side have the same structure.
In order to solve the above problem, a technology as illustrated in FIG. 3 has been proposed. Specifically, the side walls of a memory transistor and a high voltage transistor HVTr have the same structure. These side walls have a larger width than that of the side wall of the low voltage transistor LVTr (see, for example, patent document 1).
In patent document 1, three types of transistors are disposed at predetermined positions on a silicon substrate 201. On each of the poly-gate electrodes 205, 215, and 225 of the transistors, a first oxide film 210A, a first nitride film 210B, and a second oxide film 220 are sequentially formed by a low-temperature, low-pressure CVD method. The temperatures at which the first oxide film 210A, the first nitride film 210B, and the second oxide film 220 are formed (film forming temperature) are 640° C., 700° C., and 640° C., respectively. Subsequently, only in the low voltage transistor LVTr, the second oxide film 220 is removed by a wet etching method. Then, a dry etching method is performed to etch back the SW films of all of the transistors. Accordingly, the memory transistor and the high voltage transistor HVTr have a two-layered structure including a first side wall 210 and a second side wall (second oxide film) 220 positioned outside the first side wall 210, while the low voltage transistor LVTr has only the first side wall 210. Forming the three types of SW films at a low temperature prevents degrading (Ids degradation) of the electric properties of the low voltage transistor LVTr.
In the example illustrated in FIG. 3, the memory transistor is a floating gate type transistor including a tunnel insulating film 202, a floating gate 203, an ONO (oxide-nitride-oxide) film 204, and a control gate 205. The high voltage transistor HVTr and the low voltage transistor LVTr are field-effect transistors including gate electrodes 215 and 225 that are provided on the same substrate 201 via gate insulating films 212 and 222, respectively.
Patent document 1: Japanese Laid-Open Patent Application No. 2004-349680
In patent document 1, the SW width of the miniaturized low voltage transistor LVTr is smaller than that of the memory transistor or the high voltage transistor HVTr, and therefore the performance of the low voltage transistor LVTr is improved. However, when the three types of transistors are formed at once, all of the first side walls 210 in contact with side walls of the gate electrodes (including laminated gate electrode) is formed at a low temperature, in accordance with the temperature for forming the low voltage transistor LVTr. Accordingly, it is difficult to ensure data saving properties.